Seminar by Dr. Yin Chongxian

The overview of SINAP timing system: by Dr. Yin Chongxian (Electronic Group, SSRF/SINAP, Shanghai)
on April 24, 2012, 15:30-16:30, at KEKB Meeting room.; Presentation: [Pdf], [PowerPoint]; Abstract:
Recent status of the SINAP timing system is presented with the comparison of system structure and performance between version 1 and version 2.

The development of SINAP timing system and upgrading: by Dr. Yin Chongxian (Electronic Group, SSRF/SINAP, Shanghai)
on January 7, 2011, 15:00-16:00, at KEKB Meeting room.; Presentation: [Pdf], [PowerPoint]; Abstract:
Thanks to the rapid development of high speed serial communication technology, the event timing system is the more and more sophisticated solution for timing system in accelerator facilities. Based on the event timing system structure, SINAP timing system provide a complete lists of hardware which could satisfied different requirement in accelerator’s timing system. The hardware of SINAP timing system includes EVG, EVR, EVR TTL VME transition board, EVR Optic VME transition board, FANOUT, Multimode fiber O/E, Optic fiber O/E. The 2.5Gbps fiber star network is implemented in SINAP timing system, on which EVG could broadcast all triggers and clocks in this fiber network. In the upgraded SINAP timing system, the data transfer function and fiber length compensation function will be added by the dedicated data frame format. The EVRs could exchange data with the fixed latency in the upgraded SINAP timing system. The potential implementations are the global orbit feedback system, the distributed fast interlock system and so on.

Development Status of SINAP Timing System: IPAC13 WEPME032
A New Timing System: The Real Time Synchronized Data Bus: IPAC10 TUPEA032
SSRF Fast Orbit Feedback System Design and Commissioning: ICALEPCS09 THP055
The SSRF Timing System: EPAC08 THPC162
Beam Instrumentation System Development and Commissioning in SSRF: EPAC08 TUPC017
Digital Phase Control System for SSRF Linac: ICALEPCS07 FOAB02